1. Field of the Invention
This invention relates generally to a nitride-based field effect transistor (FET) device employing a plurality of dielectric passivation layers and, more particularly, to a nitride-based FET device including at least two dielectric passivation layers deposited on semiconductor device layers, where two of the passivation layers are made of different materials so that an interface between the layers acts as an etch stop to accurately control the distance between a gate terminal and the semiconductor device layers.
2. Discussion of the Related Art
Due to the wide bandgap and high carrier saturation velocity, nitride-based FET devices are ideal for high frequency and high power applications. However, these devices have had limited performance because they can suffer from electron trapping near the device surface and high gate terminal current leakage.
Dispersion or current collapse caused by electrons trapped at the surface of the semiconductor device near the gate terminal edge reduces the achievable power performance of nitride-based FET devices. In addition, under high bias conditions, the high electric fields near the gate terminal edge during device operation can cause trap formation and increases dispersion during device operation leading to premature degradation of the power performance. One widely accepted model for dispersion is that electrons injected into trap states near the gate terminal form an extended virtual gate near the gate terminal edge extending the depletion region of the device channel. Since the response of the depletion region relies on electrons being removed from trap states, the device will not respond as fast as the depletion region under the gate terminal. This effectively results in reduced power of the device under high frequency operation.
It has been reported in the literature that device dispersion can be reduced by depositing a dielectric passivation layer, such as silicon nitride (SiN), over the device after ohmic and gate contacts have been formed. Typically, without the passivation layer deposited in the access regions between the source and gate contacts and the gate and drain contacts, devices can experience nearly total current collapse or 100% dispersion. Studies have shown that dispersion can be reduced by optimization of the surface preparation before passivation layer deposition and by the quality of the passivation deposition itself. Other studies have shown that by using a SiN first process where SiN is deposited before fabrication process, the dispersion can be reduced compared to depositing the SiN after the gate and ohmic contacts have been formed. The improvement in performance has been attributed to the protection the passivation layer in the SiN first process affords the surface during device fabrication. Furthermore, other studies have shown that utilizing a SiN first process where the SiN is deposited in-situ without exposing the semiconductor layers to the air environment nearly eliminates dispersion completely. This body of evidence indicates that traps effecting dispersion occur at or near the surface of the access region of the device. This evidence also indicates that processing steps, such as ohmic anneals, plasma cleans, etc., can induce traps in the unprotected device surface.
High gate leakage current reduces power performance and can lead to premature failure an FET device. Nitride-based FET devices typically suffer from high gate leakage due to extended defects in a barrier layer of the device or traps along the surface of the FET device.
Some prior art nitride-based FET devices have utilized a MISFET type structure where a thin dielectric layer is left under the gate terminal to reduce gate current leakage problems. The dielectric layer increases the barrier to tunneling and reduces the gate current leakage. In addition it has been shown that utilizing a thin SiN dielectric layer under the gate terminal can improve reliability of the device and drastically improve the gate current stability of the device.